S.Jagadeesh, S.Venkata Chary

In this paper, we proposed a new architecture of multiplier-and-accumulator (MAC) for high-speed arithmetic By combining multiplication with accumulation and devising a hybrid type of carry save adder (CSA), the performance was improved. But using SPST(Spurious Power Suppression Technique) we can reduce power and the overall performance was elevated. The proposed SPST based radix-4 modified Booth’s algorithm (MBA) and has the modified array for the sign extension in order to increase the bit density of the operands. The Booth's radix-4 algorithm, Modified Booth Multiplier improves speed of Multipliers and SPST adder will reduce the power consumption in addition process. Also, the proposed MAC accumulates the intermediate results in the type of sum and carrybits instead of the output of the final adder. Based on the theoretical and experimental estimation, we analyzed the results such as the amount of hardware resources, delay, and power. We expect that the proposed MAC can be adapted to various fields requiring high performance such as the signal processing areas.